The present invention relates to a beam scanning type inspecting apparatus for performing inspection by scanning a beam.
JP-A-5-258703 (U.S. patent application Ser. No. 710,351 filed on May 30, 1991. Continuation application matured to U.S. Pat. No. 5,502,306) describes an apparatus for automatic inspection of X-ray masks and other conductive substrates. In the inspecting system, an electron beam image obtained by scanning a mask with an electron beam is compared with a reference to detect a defect. The inspecting system has detection modes which are a die/die mode for comparison between two dice and a die/database mode for comparison of a die with a database of a CAD.
For the sake of scanning the electron beam, the inspecting system has a deflector controller and an analog deflection circuit.
The deflector controller calculates a desired movement of a stage and sends a signal corresponding to the amount of movement to a stage servo. The deflector controller also calculates a desired deflection of the beam and sends its data to the analog deflection circuit.
The data sent from the deflector controller to the analog deflection circuit indicates a slope value which is an inclination amount of a ramp wave and this digital signal is converted into an analog voltage by means of the analog deflection circuit. A ramp generator generates the ramp wave on the basis of the analog voltage. In the inspecting system, controllable state quantities are the slope value indicative of the inclination amount of the ramp wave and a retrace value indicative of the amount of swing return of the ramp wave. The inclination amount of the analog signal designated by the slope value is compared with a line size value which is an adjusting value and an offset value designated by the retrace value is compared with an biased value which is an adjusting value. Comparison results are fed back in an analog fashion. An information fetching position is prescribed by using an external inspection start/end signal.
The scheme in which the deflection circuit is constructed of an analog integrating circuit as in this inspecting system will hereinafter be called an analog scheme.
On the other hand, with the miniaturization technology advanced, an integrated circuit manufactured by utilizing the inspecting system as above is designed at present such that for example, a 256 mega DRAM has a line width of about 0.25 xcexcm. Concomitantly with the miniaturization, inspection of particles and pattern defect has been considered to be more important in present-day inspecting apparatus than in the conventional inspecting apparatus.
But the analog deflection scheme employed in the conventional inspecting system faces problems as below.
In the analog deflection scheme, a high-precision analog integrating circuit is used to conduct a constant operation which is required of high linearity. But because of leakage current in operational amplifiers, capacitors and resistors, the linearity is distorted and the distortion is difficult to correct.
Further, only a portion of less linearity error is used by using the external inspection start/end signal, thus raising a problem that a positional difference is caused by a difference in time accuracy between a start/end signal generator circuit and an analog signal generator circuit.
Further, the accuracy is sometimes compensated by an analog feedback loop and in that case, an error is caused during a time interval which starts immediately after the setting is changed and ends when stabilization is reached, making it impossible to deal with high-speed setting change.
Further, in general, there exists biased distortion due to non-uniform electric fields and magnetic fields in the deflector and the column of the inspecting apparatus but the biased distortion is difficult to correct in the analog scheme.
Especially, when pattern comparison for separate sites as represented by chip comparison inspection is carried out, differences in large positional offset attributable to cumulation of errors and in error and distortion of arrangement (rotation and size) caused when drawing is performed on two patterns to be compared cannot be corrected, with the result that the positional accuracy matters and disadvantageously, the comparison inspection cannot proceed satisfactorily.
Further, because of difficulties in the distortion correction, a site subject to non-uniform biased distortion as represented by the wafer outer periphery cannot be inspected.
In addition, when conducting the pattern comparison inspection for the separate sites without changing and correcting the setting, elimination of distortion and maintenance of high accuracy are required for the whole of the apparatus, especially, for the optical system, the deflection unit and deflector and the stage inclusive of its control system. As a result, the cost is raised as a whole and the fabrication term is elongated in connection with tuning owing to difficulties in keeping accuracies caused by the distortion and errors.
Further, when the wafer size is increased, for example, when the wafer diameter is increased to 12 inches to increase the inspection area, the demand for high speed and high accuracy is accelerated.
On the other hand, in realizing a high-speed high-precision digital operation processor, problems as below are encountered.
To conduct a high-precision high-speed operation, real number operation processes must be executed in a parallel pipe line fashion and a great number of transistors are needed. In addition, since the real number operation process is interlinked to a controller operative on real time, it is necessary to keep the latency small in the process and besides, from the standpoint of reduction of wiring, the construction must be compact. Therefore, a very highly integrated LSI or electronic board must be materialized and high-quality logic design technology and transistor number reduction technology are required.
To meet the above requirements, many transistors in a small area are frequently subjected to switching operation and concomitantly, a large amount of heat will be generated. Circuit design for suppressing heat generation must be contrived.
However, this leads to a large-scale and complicated circuit construction which is costly.
Also, smooth interchange of information must be effected in synchronism with a high-speed clock between a master processor and the high-speed digital operation processor. A conventional means using a 2-port memory faces problems of limited access speed and access conflict of memory devices and the high-speed operation is difficult to achieve.
Further, to apply a command value to a subject to be controlled, high-precision high-speed control output operation data must be converted into a predetermined analog signal.
In the digital/analog conversion, however, restriction is imposed on the high-speed high-precision digital/analog converter. More particularly, it is difficult to deliver a result of the operation process, with its error component corrected, in the form of high-precision digital data at a clock period of, for example, 10 ns or less with an accuracy of 12 bits or more, and the operation speed cannot be increased to above that level.
On the other hand, in an electron beam drawing apparatus, a deflection control system of digital scheme is adopted as described in, for example, JP-A-5-226234. The deflection in the electron beam drawing apparatus is of the multi-stage deflection type and the deflection type per se differs from that in the inspecting apparatus. Also, the demand for high-speed operation is less stringent in the drawing apparatus than in the inspecting apparatus but in the digital scheme of the inspecting apparatus, a correction signal must be delivered at a time point within the image fetching period. In this manner, technical idea of control is greatly different for the two kinds of apparatus and it is difficult to adopt the digital scheme of the electron beam drawing apparatus as it is in the inspecting apparatus.
An object of the present invention is to provide a high-speed high-precision beam scanning type inspecting apparatus which can make various kinds of correction with ease.
To accomplish the above object, according to an aspect of the present invention, a charged particle beam scanning type inspecting apparatus has a deflection controller for controlling the scanning position of a charged particle beam to irradiate the charged particle beam onto a predetermined beam scanning position of a subject to be inspected, fetch information from the inspection subject and inspect the inspection subject by processing the information, wherein the deflection controller delivers a digital signal for control of the scanning position of the charged particle beam at a time point within an image fetching period and converts the digital signal into an analog voltage at a time point within the image fetching period to thereby control the scanning position of the charged particle beam.
According to another aspect of the invention, a charged particle beam scanning type inspecting apparatus for irradiating a charged particle beam, fetching information of a subject to be inspected at a predetermined beam scanning position and performing an inspection by processing the information, comprises:
a correction constant calculating unit for measuring a scanning position of the beam and an inspection position on the inspection subject to calculate beam target coordinates corrected for an apparatus error, an error correction constant and a biased distortion correction constant; and
a deflection controller for performing the beam scanning,
the deflection controller including:
a deflection position operating circuit for performing an operation of the inspection position in a deflection coordinate system necessary for accurate scan of the inspection position on the inspection subject by using the beam target coordinates externally set in advance or as necessary, the error correction constant, a scan constant and present coordinates of an inspection stage; and
a biased distortion operating circuit for correcting biased distortion by using the biased distortion constant externally set in advance or as necessary and the deflection position and performing an operation of the deflection control amount necessary for accurate irradiation of the beam onto the deflection position.
With the above construction, the deflection scanning position can be corrected at a time point within the period for fetching the information from the inspection subject.
According to the invention, there is provided means for sequentially changing the biased distortion correction constant supplied to the deflection controller during inspection, and near the wafer outer periphery, that is, a portion where the biased distortion is non-uniform, a biased distortion correction constant corresponding to a wafer position measured in advance is used as the biased distortion correction constant.
With this construction, distortion at the portion where the distortion is non-uniform can be corrected.
According to the invention, the position, rotation and size of first and second patterns and optical system distortion are measured in advance to calculate a scan constant and a correction constant and during continuous inspection, scan parameters and the correction constant are changed sequentially.
Through this, even when the arrangement error and distortion differ for the patterns to be compared, accurate comparable pattern information can be obtained by correction through scanning.
According to the invention, the period is 10 ns or less.
Through this, the deflection output which exceeds 200 MHz image information fetching frequency required from the relation between the inspection time and the beam irradiation time for control of electric charge on the inspection subject can be obtained.
According to the invention, the digital value of the deflection control amount has a significant digit of 16 bits or more.
Through this, a required deflection area of 500 xcexcm2 or more and a required accuracy of 20 nm or less can be realized.
According to still another aspect of the invention, a beam scanning type inspecting apparatus has a beam light source, an optical system controller for controlling the beam state, a deflector for deflecting a beam from the beam light source, an inspection stage and inspection stage controller for detecting and controlling the position of a subject to be inspected, a deflection controller for generating a digital deflection control value corresponding to a target beam deflection position through a digital operation in accordance with position or speed information from the inspection stage and a constant set externally as necessary or in advance, an image detector for obtaining digital image information at a beam scanning position on the inspection subject in timed relationship with a timing of the beam scanning, and an image processor for processing the digital image information to inspect the inspection subject, the deflection controller comprising an inspection stage position data input unit for receiving position or speed information from the inspection stage operative at a period different from that of the deflection controller, a scanning sequence/timing control unit for managing execution of scanning sequence and timing such as a timing for fetching the image in accordance with a scan constant defining scanning of one beam, deflection position correction means for performing an operation of the inspection position in a deflection coordinate system necessary for accurate scan of the inspection position on the inspection subject, biased distortion correction means for correcting biased distortion by using the constant set externally in advance or as necessary and the deflection position and performing an operation of the deflection control amount necessary for accurate irradiation of the beam onto the deflection position, DAC input data generating means for processing the digital data indicative of the deflection control amount to cause it to correspond to a predetermined analog value and generating data supplied to one or a plurality of digital/analog converters (DAC""s) a digital/analog converting unit for converting the data into an analog value, a parameter and system managing means for performing interchange of external data, system management of the deflection controller and parameter management for setting and changing parameters, and a register unit for interchanging constants between said deflection position correction unit and/or said biased distortion correction unit being operative at a high speed at first period and said parametr/system managing unit at a lower speed than that at said first period.
With this construction, a high-speed high-precision digital operation processor can be realized which serves as the deflection control circuit of the beam scanning type inspection apparatus and which can deliver a correction signal at a time point within the image fetching period.
According to the present invention, the deflection controller includes sensor input means or means for inputting information concerning height distribution depending on the wafer position and focus correction operating means, the constant concerning the biased distortion set in the biased distortion correction means by means of the parameter managing unit is changed as the height changes, and a change in focus depending on the height change is operated by means of the focus correction operating means to correct the focus.
Through this, in any area on the wafer, a change in beam position and a change in beam size or diameter due to a change in height can be corrected, thereby ensuring that the fetched image information can always be uniform and the accuracy of image comparison when patterns of separate sites are compared can be improved.
According to the present invention, the deflection controller includes astigmatism correction operating means and focus correction operating means to correct astigmatism and focus in accordance with the deflection position calculated through the deflection position correction operation.
Through this, even in any enlarged wide deflection area, the beam diameter and beam shape can be maintained correctly, the fetched image information can always be uniform and the image comparison accuracy can be improved when patterns of separate sites are compared.
According to the present invention, the biased distortion control means includes a digital operation processor for performing a digital operation process in synchronism with a high-speed clock period, an operation of a basic unit of the operation process is carried out by a MAC operating unit having a real number multiplier and a real number adder operative in a pipe line fashion and united by combining means, and the combining means brings a final stage pipe line register serving as an output stage of the real number multiplier and an initial stage pipe line register serving as an input stage of the real number adder into the same level, and a process of the final stage of the real number multiplier and part of the initial stage of the real number adder are operated in parallel.
With this construction, since the output stage of the real number multiplier and the input stage of the real number adder are at the same level, these signals can be processed in parallel, so that the final stage of the real number multiplier need not be followed by a stage for conversion into the IEEE format and data kept in the internal format can be transferred to the succeeding stage of the real number adder.
Accordingly, there is no need of a stage for execution of conversion of the results from the multiplier into the IEEE format at the initial stage of the real number adder. Further, by virtue of the construction using the real number operating units, a significant digit of 24 bits can always be maintained.
According to the present invention, the preceeding register unit includes a digital operation processor being operative to perform a digital process in synchronism with one high-rate clock and having the inspection stage data position input unit, the scanning sequence/timing managing unit, the deflection position correction means, the biased distortion correction means, the DAC input data generating means and the DA converter, one or a plurality of processors constituting the parameter managing and system managing means and operative in synchronism with a second clock asynchronous with the high-speed clock are provided, a latch register unit of two-stage structure is provided as means for supplying data from the processors to the digital operation processor at a desired time point, a latch register of the first stage has the function of latching the data from the processors in response to a first gate signal, a latch register of the second stage has the function of latching data from the latch register of the first stage in response to a second gate signal and supplying the latched data to the digital operation processor, the first gate signal is generated on the basis of a write access signal from the processors, and the second gate signal is generated on the basis of a signal obtained by making a trigger signal, delivered out of the processors and prescribing a timing for supplying data to the digital operation processor, synchronous with the high-rate clock.
By providing the processor for processing the information changing at a low speed at a second period in the operation processor for processing the information changing at a high speed at a first period, division into a portion controlled at a low speed and a portion controlled at a high speed is effected to permit suitable control and smooth interchange of information between the portions operable at the two kinds of periods can be realized. Through this, the operation means operable to process the high-speed digital operation process can be used without being affected by the information interchange period and the digital operation process being necessary for the deflection controller of digital type of the inspecting apparatus and being capable of performing the high-speed high-precision data process can be realized.
According to the invention, the DAC input data generating means is a digital operation processor for converting digital data into analog data and delivering the analog data in synchronism with the high-rate clock period and includes means for dividing the digital data into at least two output data pieces each constructed of a continuous bit train, memory means for storing correction data corresponding to upper digit output data, at least three digital/analog converters for delivering the at least two output data pieces and analog data corresponding to correction data, means for converting the at least two output data pieces into a data format supplied to corresponding digital/analog converters, and means for matching output timings of the at least two output data pieces and the correction data, whereby analog data pieces of the at least three digital/analog converters are added in an analog fashion to generate a high-precision analog output.
With this construction, the digital operation processor being necessary for the deflection controller of the digital type deflection controller and being capable of suitably converting the digital signal subject to the high-speed operation process into the analog signal at a high speed with high precision.
Still further advantages of the present invention will become apparent to those of ordinary skill in the art upon reading and understanding the following description of the preferred embodiments.